A nonlinear CMOS current mirror circuit that uses a resistor is described in detail in Patent Document 1 (JP Patent Kokoku Publication No. JP-B-S46-16468), Patent Document 2 (JP Patent No. 2800523), Patent Document 3 (JP Patent No. 3039611), and the like, for example. As the well known CMOS current mirror circuit, a reverse Widlar current mirror circuit shown in FIG. 20 is described in the Patent Document 3 (JP Patent No. 3039611) and the like.
As for a Widlar current mirror circuit shown in FIG. 21, a circuit that uses bipolar transistors is described in Non-patent Document 1 (R. J. Widlar. ‘Some Circuit design techniques for Linear Integrated Circuits,’ IEEE Transaction on Circuit Theory, VOL. CT-12, No. 4, pp. 586-590, December 1965.), and has the name of the author of the thesis.
In the circuit shown in FIG. 21, the bipolar transistors are just replaced by MOS transistors in the circuit that was proposed nearly 40 years ago, and identification of the first patent document about this circuit has not become possible yet.
Likewise, a Nagata current mirror circuit shown in FIG. 22 is also the circuit that was proposed nearly 40 years ago (for which patent application was filed in 1966), and is now referred to as the one having the name of the inventor of the circuit, by the inventor of the present invention.
The reverse Widlar current mirror circuit shown in FIG. 20 is described in detail in the document on the patent made by the inventor of the present invention (JP Patent No. 3039611), and the like. Due to the square characteristic of the MOS transistor, an output current has a negative temperature characteristic (which is scarcely known). When the temperature becomes low, the output current increases. When the temperature becomes high, the output current decreases.
On the other hand, the Widlar current mirror circuit shown in FIG. 21 has a monotonous characteristic. When an input current is increased, an increase in an output current is gradually reduced. More specifically, it can be seen that the circuit was originally proposed to obtain a small current. Further, it is well known that the Widlar current mirror circuit has a positive temperature characteristic.
The Nagata current mirror circuit shown in FIG. 22 has a peaking characteristic rather than the monotonous characteristic described before. More specifically, an output current increases monotonously with an input current, and when the input current further increases, an increase in the output current is gradually reduced to reach the peak value of the maximum output current. Then, when the input current is further increased, the output current is gradually reduced, to the contrary. A lot of applications can be conceived for the Nagata current mirror circuit because the Nagata current mirror circuit has this peaking characteristic. However, actually, the Nagata current mirror circuit is used for an alternative to a characteristic that can be implemented by the Widlar current mirror circuit in most cases. The Nagata current mirror circuit has not been so often used for the application that uses the peaking characteristic.
The potentiality of the Nagata current mirror circuit, however, is high, so that the Nagata current mirror circuit can be used for more applications.
Namely, various applications as follows have been hitherto clarified:    (1) an alternative to the Widlar current mirror circuit used in the region of a monotonous increase characteristic    (2) regulation of current used in the vicinity of the peaking characteristic    (3) implementation of a negative feedback loop circuit used in the region of a monotonous decrease characteristic    (4) start-up circuitry
The respective input-output characteristics of the reverse Widlar current mirror circuit, Widlar current mirror circuit, and Nagata current mirror circuit as described above become similar to the characteristic of the present invention shown in FIG. 7, which will be described later.
Any of the reverse Widlar current mirror circuit, Widlar current mirror circuit, and Nagata current mirror circuit, however, has a noticeable positive or negative temperature characteristic. On the hand, in many of the applications, there is seen a case where the circuit with no temperature characteristic or a smaller temperature characteristic is better.
Further, the temperature characteristic of a resistor RI, the magnitude of a manufacturing variation of resistors (of approximately ±20% in general) that would cause a more severe influence, and a CMOS transistor manufacturing variation of resistors independent of the manufacturing variation are present. Even if the manufacturing variation of resistors is ±20%, nearly ±30% of a variation in the output current of the current mirror circuit must be allowed for. This would make it impossible to obtain a satisfactory accuracy, so that external installation of the resistor or trimming of a resistance element would be required.
Conventionally, there is not known a CMOS current mirror circuit that employs no resistor of the type described above. In term of the circuit as well, the configuration can be a simple circuit with a small circuit size as shown in FIGS. 20 to 22. Thus, the CMOS current mirror circuit that causes an MOS transistor to operate in a linear region, thereby equivalently using it as a resistor has been considered to have no advantages. However, as will be described below as embodiments of the present invention, in this CMOS current mirror circuit, it has become clear that the influence of the manufacturing variation on the circuit characteristics of the circuit can be reduced due to use of MOS transistors having the same manufacturing variation alone, and that the temperature characteristic of the circuit can be reduced due to the same temperature characteristic of the MOS transistors. Thus, this circuit has great advantages.
Further, as the CMOS reference current/voltage circuit, there is known a circuit that employs no resistor by operating the MOS transistor in the linear region and equivalently using it as the resistor. This is, however, a special example in which two MOS transistors M1 and M2 constituting a current mirror circuit are operated in weak inversion (sub-threshold region). As the CMOS reference current circuit having the positive temperature characteristic, for example, a circuit shown in FIG. 23 is disclosed in Patent Document 4 (U.S. Pat. No. 5,949,278) and Non-patent Document 2 (IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1132-1135, July 1997.) and the like.
In most cases, the MOS transistor is generally operated in a saturation region. As in an example shown in FIG. 23, the circuit is configured by causing the two MOS transistors M1 and M2 constituting the current mirror circuit to operate in weak inversion, in expectation of a characteristic just like that of the bipolar transistor. When the MOS transistor is operated in weak inversion, the current flown becomes a nA (nano-ampere) order, which is reduced from the current that can be flown through the ordinary MOS transistor operated in the saturation region by a factor of several orders of magnitude. Thus, an extreme limitation is imposed on the applications of the circuit. Accordingly, the example shown in FIG. 23 is not versatile, but a special example.
Further, when the two MOS transistors constituting the nonlinear current mirror circuit as described above are self-biased, the influence of a linear current mirror circuit used for self-biasing will appear more noticeably than the characteristic of the self-biased nonlinear current mirror circuit.
When the nonlinear current mirror circuit is self-biased, for example, the nonlinear current mirror circuit will have the positive temperature characteristic, irrespective of whether the original temperature characteristic of the nonlinear current mirror circuit is positive or negative.
Accordingly, the characteristic of the original nonlinear current circuit will sometimes become different from that of the self-biased nonlinear current mirror circuit of the same circuit, so that it often happens that these circuits cannot be treated to be the same.
Referring to FIG. 23, MOS transistors M4 and M3 constitute a current mirror circuit, while the MOS transistor M4 and an MOS transistor M5 constitute a current mirror circuit. Further, the circuit is configured so that between the source of the MOS transistor M1 and the ground, a circuit element (generally a resistance element) for restricting a flow of current, or an MOS transistor M7 in this example is operated in the linear region to be equivalently regarded as the resistance element. As described above, it is arranged that the MOS transistors M2 and M1 constitute the nonlinear current mirror circuit. That is, the reference current circuit of this type, as the simplest circuit form, is implemented by self-biasing the nonlinear current mirror circuit. By the way, though the reference current circuit of a self-biasing type always requires start-up circuitry, the start-up circuitry is omitted in this drawing.
When the MOS transistors M1 and M2 operate in weak inversion, a source voltage VS1 of the MOS transistor M1 is expressed as follows:Vm=Vr 1n(K1 K2)  (1)
where K1 indicates the transconductance parameter ratio of the MOS transistor M1 with respect to the MOS transistor M2, while k2 indicates the transconductance parameter ratio of the MOS transistor M3 with respect to the MOS transistor M4. A transconductance parameter β is expressed as β=μ (COX/2)(W/L), where μ indicates effective mobility of a carrier (of an n channel) or a hole (of a p channel). COX is the capacitance of a gate oxide film per unit area. W and L indicate a gate width and a gate length, respectively. VT which indicates a thermal voltage, is expressed as VT=kT/q (k: a Boltzmann constant, T: absolute temperature, q: the unit electronic charge).
As for the characteristic of the MOS transistor, when a drain current thereof is indicated by ID, a gate-to-source voltage thereof is indicated by VGS, a drain-to-source voltage thereof is indicated by VDS, and a threshold voltage thereof is indicated by VTH, the following equation holds in the saturation region:ID=β(VGS'VTH)2  (2)
In the linear region, the following equation holds:ID=2nβ{(VGS−VTH)VDS−nVDS2/2 }  (3)
In weak inversion, the following equations hold:ID=IS exp {(VGB−VTHo)/(nVT)}exp(−VSB/VT)  (4)IS=2n βVT2  (5)
where B indicates a back gate, VGB indicates a gate voltage with respect to the bulk, VSB indicates a source-voltage with respect to the bulk, and n indicates a correcting coefficient when a low drain-to-source voltage is applied.
Equation (2) is applied to the MOS transistor M6, while Equation (3) is applied to the MOS transistor M7. Then, the drain currents ID6 and ID7 of MOS transistors M6 and M7 are given by:ID6=K3β(VGS6−VTH)2  (6)ID7=2nK4β{(VGS6−VTH)VS1−nVS12/2}  (7)
where the transconductance parameter ratio of the MOS transistor M6 with respect to the MOS transistor M2 is indicated by K3, while the transconductance parameter ratio of the MOS transistor M7 with respect to the MOS transistor M2 is indicated by K4.
The MOS transistors M4 and MS constitute the current mirror circuit with a current ratio of one to K5. Thus, the following equation holds:ID6=K5×ID7  (8)
When (VGS6−VTH) obtained from Equation (6) is substituted into Equation (7) for solution of this, the following equation is obtained:
                              I                      D            ⁢                                                  ⁢            1                          =                  2          ⁢                      n                    ⁢                      K            4                    ⁢          β          ⁢                                          ⁢                                    V                              S                ⁢                                                                  ⁢                1                                        ⁡                          (                                                                                          K                      4                                        ⁢                                          K                      5                                                                            K                    3                                                  -                                                      1                    2                                    ±                                                                                    K                        4                                                                    K                        3                                                              ⁢                                                                  K                                                                ⁢                                                                                            K                                                  -                                                                              K                            3                                                                                K                            4                                                                                                                                                          )                                                          (        9        )            
When Equation (1) is substituted into Equation (9), the following equation is derived:
                              I                      D            ⁢                                                  ⁢            1                          =                  2          ⁢                      n                      ⁢                      K            4                    ⁢          β          ⁢                                          ⁢                      V            T            2                    ⁢                                          ⁢                                    {                              ln                ⁢                                  (                                                            K                      1                                        ⁢                                          K                      2                                                        )                                            }                        2                    ⁢                                          ⁢                      (                                                                                K                    4                                    ⁢                                      K                    5                                                                    K                  3                                            -                                                          ⁢                                                1                  2                                ±                                                                            K                      4                                                              K                      3                                                        ⁢                                                            K                                                          ⁢                                                                                    K                                              -                                                                        K                          3                                                                          K                          4                                                                                                                                          )                                              (        10        )            
The temperature characteristic of the transconductance parameter β is expressed as follows due to:
                                          μ            =                                                            μ                  0                                ⁡                                  (                                                            T                      0                                        T                                    )                                                                ⁢                                          ⁢          β                =                                            β              0                        ⁡                          (                                                T                  0                                T                            )                                m                                    (        11        )            where m in (T0/T)m assumes a value between 1.5 and 2 (1.5<m<2).
Accordingly, the following equation is obtained:
                              I                      D            ⁢                                                  ⁢            1                          =                  2          ⁢                      n            2                    ⁢                                          ⁢                      K            4                    ⁢                                          ⁢                                                    β                0                            ⁡                              (                                  T                                      T                    0                                                  )                                                ⁢                                          ⁢                                    k              2                                      q              2                                ⁢                                          ⁢                                    {                              ln                ⁡                                  (                                                            K                      1                                        ⁢                                          K                      2                                                        )                                            }                        2                    ⁢                                          ⁢                      (                                                                                K                    4                                    ⁢                                      K                    5                                                                    K                  3                                            -                                                1                  2                                ±                                                                            K                      4                                                              K                      3                                                        ⁢                                                            K                                                          ⁢                                                                                    K                                              +                                                                        K                          3                                                                          K                          4                                                                                                                                          )                    ⁢                                      (        12        )            
In the above-mentioned Equations (9), (10), and (12), a symbol ± is used so that the solutions of the equations can be traced. Referring to FIG. 23, it can be seen that as the K4 is increased, a current ID1 is increased. It is therefore appropriate to replace the symbol ± by +.
Accordingly, the current ID1 has the positive temperature characteristic. That is, it serves as a PTAT (proportional to absolute temperature) current source.                [Patent Document 1]        
JP Patent Kokoku Publication No. JP-B-S46-16468                [Patent Document 2]        
JP Patent No. 2800523                [Patent Document 3]        
JP Patent No. 3039611                [Patent Document 4]        
U.S. Pat. No. 5949278                [Non-patent Document 1]        
R. J. Widlar. “Some Circuit design techniques for Linear Integrated Circuits,” IEEE Transaction on Circuit Theory, VOL. CT-12, No. 4, pp. 586-590, December 1965.                [Non-patent Document 2]        
H. J. Oguey and D. Aebischer, “CMOS Current Reference Without Resistance,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1132-1135, July 1997.